Piet De Moor, IMEC shares his thoughts on stacked image sensors with Smithers Apex

Smithers Apex interviews Piet De Moor in the lead up to his presentation at Image Sensors Americas 2014

Q. Please briefly describe your background in digital imaging.

I have been working at new image sensor technology for the last 15 years at imec, initially mainly focusing on research and development for space imager applications (i.e. hybrid backside illuminated imagers), but the last couple of years we are doing custom imager development and low volume production of medium to high-end imagers.

Q. Stacked chip sensor designs are the topic of the moment - how big an impact do you think this type of technology will have on the image sensors market?

I expect a big impact of stacked image sensors, not so much on the image sensing quality but rather at the system integration level, which will enable smart and very compact imagers for both consumer (e.g. mobile phone) as industrial inspection and security imaging systems.

Q. What are the challenges with stacking that have not yet been addressed by the market?

There is still a way to go to improve the maturity of stacking technologies (e.g. high density wafer to wafer vertical interconnects using wafer-to-wafer bonding) in terms of yield and manufacturability. Only when these technologies will become available in (CMOS) foundries the additional cost will be low enough to enable volume manufacturing of stacked imagers.

Q. What are the main advantages of stacked sensors, and how far can we push performance boundaries with this approach?

In my opinion the top layer of a stacked imager will always be a backside illuminated pixel array, which guarantees the excellent optical performance of the current generation of backside illuminated imagers. The additional functionality offered by stacking is the potential of an area distributed pixel readout right underneath the pixel area, which allows a very fast or high dynamic range readout, a local analog-to-digital conversion, local image processing or combinations of above. Stacking will further reduce the total system cost and size as image processing and readout functionality which is now off-chip will become part of the stacked imager.

Q. You will cover some other innovations in your presentation, can you give us a brief preview of those?

At imec we are also developing other imager modules such as embedded CCD in CMOS and on-chip hyperspectral filters, which are both compatible with imager stacking, and therefore will enable a number of unique vision applications.